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ultra37000 cpld family 5 v and 3.3 v isr? high performance cplds cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 38-03007 rev. *h revised november 09, 2010 features in-system reprogrammable? (isr?) cmos cplds ? jtag interface for reconfigurability ? design changes do not cause pinout changes ? design changes do not cause timing changes high density ? 32 to 512 macrocells ? 32 to 264 i/o pins ? 5 dedicated inputs including 4 clock pins simple timing model ? no fanout delays ? no expander delays ? no dedicated vs. i/o pin delays ? no additional delay through pim ? no penalty for using full 16 product terms ? no delay for steering or sharing product terms 3.3v and 5v versions pci compatible [1] programmable bus-hold capabilities on all i/os intelligent product te rm allocator provides ? 0 to 16 product terms to any macrocell ? product term steering on an individual basis ? product term sharing among local macrocells flexible clocking ? 4 synchronous clocks per device ? product term clocking ? clock polarity control per logic block consistent package and pinout offering across all densities ? simplifies design migration ? same pinout for 3.3v and 5v devices packages ? 44 to 256 pins in plcc, pqfp, tqfp, and fine-pitch bga packages ? pb-free packages available general description the ultra37000? family of cmos cplds provides a range of high density programmable logic solutions with unparalleled system performance. the ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22v10 to high density cplds. the architecture is based on a number of logic blocks that are connected by a programmable interconnect matrix (pim). each logic block features its own product term array, product term allocator, and 16 macrocells. the pim distributes signals from the logic block outputs and all input pins to the logic block inputs. all the ultra37000 devices are electrically erasable and in-system reprogrammable (isr), which simplifies both design and manufacturing flows, ther eby reducing costs. the isr feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. the cypress isr function is implem ented through a jtag-compliant serial interface. data is shifted in and out through the tdi and tdo pins, respectively. because of the superior routability and simple timing model of the ultra37000 devices, isr allows users to change existing logic designs while simultaneously fixing pinout assignments and mainta ining system performance. the entire family features jt ag for isr and boundary scan, and is compatible with the pci local bus specification, meeting the electrical and timing requirements. the ultra37000 family features user programmable bus-hold capabilities on all i/os. ultra37000 5v devices the ultra37000 devices operate with a 5v supply and can support 5v or 3.3v i/o levels. v cco connections provide the capability of interfacing to either a 5v or 3.3v bus. by connecting the v cco pins to 5v the user insures 5v ttl levels on the outputs. if v cco is connected to 3.3v th e output levels meet 3.3v jedec standard cmos levels and are 5v tolerant. these devices require 5v isr programming. ultra37000v 3.3v devices devices operating with a 3.3v supply require 3.3v on all v cco pins, reducing the device?s power consumption. these devices support 3.3v jedec standard cmos output levels, and are 5v-tolerant. these devices allow 3.3v isr programming. note 1. due to the 5v tolerant nature of 3.3v device i/os, the i/os are not clamped to v cc , pci v ih = 2v. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 2 of 43 contents features ............................................................................. 1 general description ......................................................... 1 ultra37000 5v devices ........... ............................ ......... 1 ultra37000v 3.3v devices ..... ............................ ......... 1 contents ............................................................................ 2 selection guide ................................................................ 3 5v selection guide ...................................................... 3 3.3v selection guide ................................................... 3 architecture overview of ul tra37000 family ........... ...... 4 programmable interconnect matr ix ............................. 4 logic block .................................................................. 4 product term allocator ........... ..................................... 5 ultra37000 macrocell ............. ............................ ......... 5 clocking ....................................................................... 7 timing model ............................................................... 7 jtag and pci standards ................................................. 8 pci compliance .......................................................... 8 ieee 1149.1-compliant jtag ... ......................... ......... 8 development software support ...................................... 8 warp ............................................................................ 8 warp professional ? ................................................... 8 warp enterprise ? ....................................................... 8 third-party software ................................................... 8 programming ............................................................... 8 third-party programme rs ............................................ 9 logic block diagrams .................................................... 10 5v device maximum ratings ......................................... 13 operating range.............................................................. 13 5v device electrical characteristics over the operating range ............................................................................... 13 inductance........................................................................ 14 capacitance ..................................................................... 14 endurance characteristics ............................................. 14 3.3v device maximum ratings ...................................... 14 operating range.............................................................. 14 3.3v device electrical characteristics over the operating range ............................................................................... 14 inductance........................................................................ 15 capacitance ..................................................................... 15 endurance characteristics ............................................. 15 ac characteristics ......................................................... 15 switching characteristics over the operating range .. 16 switching characteristics over the operating range .. 18 switching waveforms .................................................... 19 power consumption ....................................................... 23 typical 5v power consumption ................................ 23 typical 3.3v power consumption ............................. 26 pin configurations .......................................................... 29 ordering information ...................................................... 34 5v ordering information ................................................ 34 3.3v ordering information ............................................. 35 addendum ....................................................................... 35 3.3v operating range ............................................... 35 package diagrams .......................................................... 36 document history page ................................................. 40 sales, solutions, and legal information ...................... 43 worldwide sales and design s upport ......... .............. 43 products .................................................................... 43 psoc solutions ......................................................... 43 [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 3 of 43 selection guide 5 v selection guide table 1. general information device macrocells dedicated inputs i/o pins speed (t pd ) speed (f max ) cy37032 32 5 32 6 200 cy37064 64 5 32/64 6 200 cy37128 128 5 64/128 6.5 167 cy37192 192 5 120 7.5 154 cy37256 256 5 128/160/192 7.5 154 table 2. speed bins device 200 167 154 125 100 83 cy37032 x x cy37064 x x x cy37128 x x x cy37192 x x cy37256 x x table 3. device-package offering and i/o count device 44-pin tqfp 44-pin plcc 100-pin tqfp 160-pin tqfp cy37032 37 37 cy37064 37 37 69 cy37128 69 133 cy37192 125 cy37256 133 3.3 v selection guide table 4. general information device macrocells dedicated inputs i/o pins speed (t pd ) speed (f max ) cy37032v 32 5 32 8.5 143 cy37064v 64 5 32/64 8.5 143 cy37128v 128 5 64/80/128 10 125 cy37192v 192 5 120 12 100 cy37256v 256 5 128/160/192 12 100 table 5. speed bins device 143 125 100 83 66 cy37032v x x cy37064v x x cy37128v x x cy37192v x x cy37256v x x table 6. device-package offering and i/o count device 44-pin tqfp 100-pin tqfp 160-pin tqfp 256-pin fbga cy37032v 37 cy37064v 37 69 cy37128v 69 133 cy37192v 125 cy37256v 133 197 [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 4 of 43 architecture overview of ultra37000 family programmable interconnect matrix the pim consists of a completely global routing matrix for signals from i/o pins and feedbacks from the logic blocks. the pim provides extremely robust interconnection to avoid fitting and density limitations. the inputs to the pim consist of all i/o and dedicated input pins and all macrocell feedbacks from within the logic blocks. the number of pim inputs increases with pin count and the number of logic blocks. the outputs from the pim are signals routed to the appropriate l ogic blocks. each logic block receives 36 inputs from the pim and their complements, allowing for 32-bit opera- tions to be implemented in a single pass through the device. the wide number of inputs to the logic block also improves the routing capacity of the ultra37000 family. an important feature of the pim is its simple timing. the propa- gation delay through the pim is a ccounted for in the timing speci- fications for each device. there is no additional delay for traveling through the pim. in fact, all inputs travel through the pim. as a result, there are no route-dependent timing param- eters on the ultra37000 devices. the worst-case pim delays are incorporated in all appropria te ultra37000 specifications. routing signals through the pim is completely invisible to the user. all routing is accomplished by software?no hand routing is necessary. warp ? and third-party development packages automatically route designs for the ultra37000 family in a matter of minutes. finally, the rich routing resources of the ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments. logic block the logic block is the basic building block of the ultra37000 architecture. it consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of i/o cells. the number of i/o cells varies depending on the device used. refer to figure 1 for the block diagram. product term array each logic block features a 72 x 87 programmable product term array. this array accepts 36 inputs from the pim, which originate from macrocell feedbacks and device pins. active low and active high versions of each of these inputs are generated to create the full 72-input field. the 87 product terms in the array can be created from any of the 72 inputs. of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. four of the remaining seven product terms in the logic block are output enable (oe) product terms. each of the oe product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. in other words, each i/o cell can select between one of two oe product terms to control the output buffer. the first two of these four oe product terms are available to the upper half of the i/o macrocells in a logic block. the other two oe product terms are available to the lower half of the i/o macrocells in a logic block. the next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. the final product term is the product term clock. the set, reset, oe and product term clock have polarity control to realize or functions in a single pass through the array. figure 1. logic block with 50% buried macrocells i/o cell 0 product term allocator i/o cell 14 macro- cell 0 macro- cell 1 macro- cell 14 0?16 product terms 72 x 87 product term array 80 36 8 16 to pim from pim 7 3 2 macro- cell 15 2 to cells 2, 4, 6 8, 10, 12 0 ?16 product terms 0? 16 product terms 0?16 product terms [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 5 of 43 low power option each logic block can operate in high speed mode for critical path performance, or in low power mode for power conservation. the logic block mode is set by the user on a logic block by logic block basis. product term allocator through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. a total of 80 product terms are available from the local product term array. the product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. product term steering product term steering is the process of assigning product terms to macrocells as needed. for example, if one macrocell requires ten product terms while another needs just three, the product term allocator will ?steer? ten product terms to one macrocell and three to the other. on ultra37000 devices, product terms are steered on an individual basis. any number between 0 and 16 product terms can be steered to any macrocell. note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. product term sharing product term sharing is the process of using the same product term among multiple macrocells. for example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. the ultra37000 product term allocator allows sharing across groups of four output macrocells in a variable fashion. the software automatically takes advantage of this capability?the user does not have to intervene. note that neither product term sharing nor product term steering have any effect on the speed of the product. all worst-case steering and sharing configurati ons are incorporated in the timing specifications for the ultra37000 devices. ultra37000 macrocell within each logic block there are 16 macrocells. macrocells can either be i/o macrocells, which include an i/o cell which is associated with an i/o pin, or buried macrocells, which do not connect to an i/o. the combination of i/o macrocells and buried macrocells varies from device to device. buried macrocell figure 2 displays the architecture of buried macrocells. the buried macrocell features a regi ster that can be configured as combinatorial, a d flip-flop, a t f lip-flop, or a level-triggered latch. the register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. each of these product terms features programmable polarity. this allows the registers to be set or reset based on an and expression or an or expression. clocking of the register is very flexible. four global synchronous clocks and a product term clock are available to clock the register. furthermore, each clock features programmable polarity so that registers can be triggered on falling and rising edges (see clocking on page 7). clock polarity is chosen at the logic block level. the buried macrocell also supports input register capability. the buried macrocell can be configured to act as an input register (d-type or latch) whose input comes from the i/o pin associated with the neighboring macrocell. the output of all buried macro- cells is sent directly to the pi m regardless of its configuration. i/o macrocell figure 2 illustrates the architecture of the i/o macrocell. the i/o macrocell supports the same f unctions as the buried macrocell with the addition of i/o capability . at the output of the macrocell, a polarity control mux is available to select active low or active high signals. this has the added advantage of allowing signif- icant logic reduction to occur in many applications. the ultra37000 macrocell features a feedback path to the pim separate from the i/o pin input path. this means that if the macrocell is buried (fed back inter nally only), the associated i/o pin can still be used as an input. bus hold capabilities on all i/os bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latc h connected to the pin that does not degrade the device?s perfor mance. as a latch, bus-hold maintains the last state of a pin when the pin is placed in a high impedance state, thus reducing system noise in bus-interface applications. bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. for more information, see the application note understanding bus-hold?a feature of cypress cplds . programmable slew rate control each output has a programmable configuration bit, which sets the output slew rate to fast or slow. for designs concerned with meeting fcc emissions standards the slow edge provides for lower system noise. for designs requiring very high performance the fast edge rate provides maximum system performance. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 6 of 43 figure 2. i/o and buried macrocells figure 3. input macrocell c2 c3 decode c2 c3 decode 0 1 2 3 o c6 c5 ?0? ?1? 0 1 o d/t/l q r p 0 1 2 3 o c0 0 1 o c4 feedback to pim feedback to pim block reset 0 ? 16 terms i/o macrocell i/o cell from ptm 0 1 o d/t/l q r p from ptm 1 o c7 feedback to pim buried macrocell 0 asynchronous product 0 ? 16 terms product c1 4 0 1 2 3 q 4 c24 c0 c1 c24 c25 c25 4 synchronous clocks (clk0,clk1,clk2,clk3) 1 asynchronous clock(ptclk) block preset asynchronous fast slow c26 slew 0 1 0 1 0 1 0 1 oe0 oe1 0 1 2 3 o c12 c13 to pim d q d q d q le input pin 0 1 2 o c10 from clock polarity muxes 3 c11 [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 7 of 43 figure 4. input/clock macrocell clocking each i/o and buried macrocell has access to four synchronous clocks (clk0, clk1, clk2 and clk3) and an asynchronous product term clock ptclk. each input macrocell has access to all four synchronous clocks. dedicated inputs/clocks five pins on each member of the ultra37000 family are designated as input-only. there are two types of dedicated inputs on ultra37000 devices: input pins and input/clock pins. figure 3 illustrates the architecture for input pins. four input options are available for the user: combinatorial, registered, double-registered, or la tched. if a registered or latched option is selected, any one of the input cl ocks can be selected for control. figure 4 illustrates the architecture for the input/clock pins. similar to the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. in addition, these pins feed the clocking structures throughout the device. the clock path at the input has user-configurable polarity. product term clocking in addition to the four synchronous clocks, the ultra37000 family also has a product term clock fo r asynchronous clocking. each logic block has an independent product term clock which is available to all 16 macrocells. each product term clock also supports user configurable polarity selection. timing model one of the most important featur es of the ultra37000 family is the simplicity of its timing. al l delays are worst case and system performance is unaffected by the features used. figure 5 illustrates the true timing model for the 167-mhz devices in high speed mode. for combinatorial paths, any input to any output incurs a 6.5 ns worst-case delay regardless of the amount of logic used. for synchronous systems, the input setup time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. these m easurements are for any output and synchronous clock, regardless of the logic used. the ultra37000 features: no fanout delays no expander delays no dedicated vs. i/o pin delays no additional delay through pim no penalty for using 0?16 product terms no added delay for steering product terms no added delay for sharing product terms no routing delays no output bypass delays the simple timing model of the ultra37000 family eliminates unexpected performance penalties. figure 5. timing model for cy37128 0 1 2 3 o c10c11 to pim d q d q d q le input/clock pin 0 1 2 o from clock clock pins 0 1 o c12 to clock mux on all input macrocells to clock mux in each 3 0 1 clock polarity mux one per logic block for each clock input polarity input logic block c8 c9 c13, c14, c15 or c16 o combinatorial signal registered signal d,t,l o clock input input output output t s = 3.5 ns t co = 4.5 ns t pd = 6.5 ns [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 8 of 43 jtag and pci standards pci compliance 5v operation of the ultra37000 is fully compliant with the pci local bus specification published by the pci special interest group. the 3.3v products meet a ll pci requirements except for the output 3.3v clamp, which is in direct conflict with 5v tolerance. the ultra37000 family?s simple and predictable timing model ensures compliance with the pci ac specifications independent of the design. ieee 1149.1-compliant jtag the ultra37000 family has an ieee 1149.1 jtag interface for both boundary scan and isr. boundary scan the ultra37000 family supports bypass, sample/preload, extest, idcode, and usercode bo undary scan instructions. the jtag interface is shown in figure 6 . figure 6. jtag interface in-system reprogramming (isr) in-system reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. this combination means design changes during debug or field upgrades do not cause board respins. the ultra37000 family implements isr by providing a jtag compliant interface for on-boar d programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. development software support warp warp is a state-of-the-art compiler and complete cpld design tool. for design entry, warp provides an ieee-std-1076/1164 vhdl text editor, an ieee-std-1364 verilog text editor, and a graphical finite state machine editor. it provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target de vice, by implementing logic in unused memory and by perfect communication between fitting and synthesis. to facilitate design and debugging, warp provides graphical timing simulation and analysis. warp professional ? warp professional contains several additional features. it provides an extra method of des ign entry with its graphical block diagram editor. it allows up to 5 ms timing simulation instead of only 2 ms. it allows comparison of waveforms before and after design changes. warp enterprise ? warp enterprise provides even more features. it provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. it has the ability to generate graphical hdl blocks from hdl text. it can even generate testbenches. warp is available for pc and unix platforms. some features are not available in the unix version. for further information see the warp for pc , warp for unix, warp professional and warp enterprise data sheets on cypress?s web site. third-party software although warp is a complete cpld development tool on its own, it interfaces with nearly every third party eda tool. all major third-party software vendors provide support for the ultra37000 family of devices. refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors. programming there are four programming options available for ultra37000 devices. the first method is to use a pc with the 37000 ultraisr programming cable and software. with this method, the isr pins of the ultra37000 devices are ro uted to a connector at the edge of the printed circuit board. the 37000 ultraisr programming cable is then connected between th e parallel port of the pc and this connector. a simple configuration file instructs the isr software of the programming operations to be performed on each of the ultra37000 devices in the system. the isr software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other isr functions. for more information on the cypress isr interface, see the cyusbisrpc programming cable user?s guide. instruction register boundary scan idcode usercode isr prog. bypass reg. data registers jtag tap controller tdo tdi tms tck [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 9 of 43 the second method for programming ultra37000 devices is on automatic test equipment (ate). this is accomplished through a file created by the isr software . check the cypress website for the latest isr software download information. the third programming option for ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. the ultra37000 isr software assists in this method by converting the device jedec maps into the isr serial stream that contains the is r instruction information and the addresses and data of locations to be programmed. the embedded controller then simply directs this isr stream to the chain of ultra37000 devices to complete the desired reconfiguring or diagnostic operations. contact your local sales office for infor- mation on availability of this option. the fourth method for programming ultra37000 devices is to use the same programmer that is currently being used to program f lash 370i devices. for all pinout, electrical, and timing requirements, refer to device data sheets. for isr cable and software specifications, refer to the ultraisr kit data sheet (cy3700i). third-party programmers as with development software, cypress support is available on a wide variety of third-party prog rammers. all major third-party programmers (including bp micro, data i/o, and sms) support the ultra37000 family. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 10 of 43 logic block diagrams cy37032/cy37032v logic block b logic block a 36 16 36 16 input clock/ input 16 i/os 16 i/os i/o 0 ? i/o 15 i/o 16 ? i/o 31 4 4 4 16 16 tdi tck tms tdo jtag tap controller 1 pim jtag en logic block d logic block c logic block a logic block b 36 16 36 16 36 16 36 16 input clock/ input 16 i/os 16 i/os 16 i/os 16 i/os i/o 0 -i/o 15 i/o 16 -i/o 31 i/o 48 -i/o 63 i/o 32 -i/o 47 4 4 4 32 32 tdi tck tms tdo jtag tap controller 1 pim cy37064/cy37064v [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 11 of 43 logic block diagrams (continued) tdi tck tms tdo jtag tap controller cy37128/cy37128v pim input macrocell clock inputs 4 4 36 16 16 36 logic block 36 16 16 36 16 i/os 36 36 36 16 16 36 16 16 64 64 4 1 input/clock macrocells i/o 0 ?i/o 15 a inputs logic block c logic block b logic block d logic block h logic block g logic block f logic block e i/o 16 ?i/o 31 i/o 32 ?i/o 47 i/o 28 ?i/o 63 i/o 112 ?i/o 127 i/o 96 ?i/o 111 i/o 80 ?i/o 95 i/o 64 ?i/o 79 16 i/os 16 i/os 16 i/os 16 i/os 16 i/os 16 i/os 16 i/os jtag en logic block h logic block l logic block i logic block j logic block k logic block a logic block b logic block c logic block d logic block e logic block g logic block f 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 pim input clock/ input 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os i/o 0 ?i/o 9 i/o 10 ?i/o 19 i/o 20 ?i/o 29 i/o 30 ?i/o 39 i/o 40 ?i/o 49 i/o 50 ?i/o 59 i/o 110 ?i/o 119 i/o 100 ?i/o 109 i/o 90 ?i/o 99 i/o 80 ?i/o 89 i/o 70 ?i/o 79 i/o 60 ?i/o 69 4 4 4 60 60 tdi tck tms tdo jtag tap controller 1 cy37192/cy37192v [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 12 of 43 logic block diagrams (continued) cy37256/cy37256v logic block g logic block h logic block i logic block j logic block l logic block p logic block m logic block n logic block o logic block a logic block b logic block c logic block d logic block e logic block k logic block f 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 pim input clock/ input 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os i/o 0 ? i/o 11 i/o 12 ? i/o 23 i/o 24 ? i/o 35 i/o 36 ? i/o 47 i/o 48 ? i/o 59 i/o 60 ? i/o 71 i/o 72 ? i/o 83 i/o 84 ? i/o 95 i/o 180 ? i/o 191 i/o 168 ? i/o 179 i/o 156 ? i/o 167 i/o 144 ? i/o 155 i/o 132 ? i/o 143 i/o 120 ? i/o 131 i/o 108 ? i/o 119 i/o 96 ? i/o 107 4 4 4 96 96 tdi tck tms tdo jtag tap controller 1 [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 13 of 43 5v device maxi mum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied ............ ............................. ... ?55c to +125c supply voltage to ground potentia l................?0.5v to +7.0v dc voltage applied to outputs in high-z state......................... .......................?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v dc program voltage............................................. 4.5 to 5.5v current into outputs .................................................... 16 ma static discharge voltage....... ........... ............ ............. > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range [2] range ambient temperature [2] junction temperature output condition v cc v cco commercial 0c to +70c 0c to +90c 5v 5v ? 0.25v 5v ? 0.25v 3.3v 5v ? 0.25v 3.3v ? 0.3v industrial ?40c to +85c ?40c to +105c 5v 5v ? 0.5v 5v ? 0.5v 3.3v 5v ? 0.5v 3.3v ? 0.3v 5v device electrical characteristics over the operating range parameter description test conditions min typ max unit v oh output high voltage v cc = min i oh = ?3.2 ma (com?l/ind) [4] 2.4 v i oh = ?2.0 ma (mil) [4] 2.4 v v ohz output high voltage with output disabled [5] v cc = max i oh = 0 ? a (com?l) [6] 4.2 v i oh = 0 ? a (ind/mil) [6] 4.5 v i oh = ?100 ? a (com?l) [6] 3.6 v i oh = ?150 ? a (ind/mil) [6] 3.6 v v ol output low voltage v cc = min i ol = 16 ma (com?l/ind) [4] 0.5 v i ol = 12 ma (mil) [4] 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs [7] 2.0 v ccmax v v il input low voltage guaranteed input logical low voltage for all inputs [7] ?0.5 0.8 v i ix input load current v i = gnd or v cc , bus-hold disabled ?10 10 ? a i oz output leakage current v o = gnd or v cc , output disabled, bus-hold disabled ?50 50 ? a i os output short circuit current [5, 8] v cc = max, v out = 0.5v ?30 ?160 ma i bhl input bus-hold low sustaining current v cc = min, v il = 0.8v +75 ? a i bhh input bus-hold high sustaining current v cc = min, v ih = 2.0v ?75 ? a i bhlo input bus-hold low overdrive current v cc = max +500 ? a i bhho input bus-hold high overdrive current v cc = max ?500 ? a notes 2. normal programming conditions apply across ambient temperature range for specified programming methods. for more information on programming the ultra37000 family devices, refer to the application note titled an introduction to in system reprogramming with the ultra37000 . 3. t a is the ?instant on? case temperature. 4. i oh = ?2 ma, i ol = 2 ma for tdo. 5. tested initially and after any design or process changes that may affect these parameters. 6. when the i/o is output disabled, the bus- hold circuit can weakly pull the i/o to abov e 3.6v if no leakage current is allowed. note that all i/os are output disabled during isr programming. refer to the application note ?understanding bus-hold? for additional information. 7. these are absolute values with respect to device ground. all overshoots due to system or tester noise are included. 8. not more than one output should be tested at a time. dura tion of the short circuit should not exceed 1 second. v out = 0.5v is chosen to av oid test problems caused by tester ground degradation. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 14 of 43 3.3v device maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 ? c to +150 ?c ambient temperature with power applied ............................................ ?55 ? c to +125 ?c supply voltage to ground potentia l................?0.5v to +4.6v dc voltage applied to outputs in high-z state......................... .......................?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v dc program voltage............................................. 3.0 to 3.6v current into outputs ...................................................... 8 ma static discharge voltage....... ........... ............ ............. > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma inductance [5] parameter description test conditions 44-pin tqfp 44-pin plcc 100-pin tqfp 160-pin tqfp unit l maximum pin inductance v in = 5v at f = 1 mhz 2 5 8 9 nh capacitance [5] parameter description test conditions max unit c i/o input/output capacitance v in = 5v at f = 1 mhz at t a = 25c 10 pf c clk clock signal capacitance v in = 5v at f = 1 mhz at t a = 25c 12 pf c dp dual-function pins [9] v in = 5v at f = 1 mhz at t a = 25c 16 pf endurance characteristics [5] parameter description test conditions min typ unit n minimum reprogramming cycles normal programming conditions [2] 1,000 10,000 cycles operating range [2] range ambient temperature [2] junction temperature v cc [10] commercial 0c to +70c 0c to +90c 3.3v 0.3v industrial ?40c to +85c ?40c to +105c 3.3v 0.3v 3.3v device electri cal characteristics over the operating range parameter description test conditions min max unit v oh output high voltage v cc = min i oh = ?4 ma (com?l) [4] 2.4 v i oh = ?3 ma (mil) [4] v ol output low voltage v cc = min i ol = 8 ma (com?l) [4] 0.5 v i ol = 6 ma (mil) [4] v ih input high voltage guaranteed input logical high voltage for all inputs [7] 2.0 5.5 v v il input low voltage guaranteed input logical low voltage for all inputs [7] ?0.5 0.8 v i ix input load current v i = gnd or v cc , bus-hold disabled ?10 10 ? a i oz output leakage current v o = gnd or v cc , output disabled, bus-hold disabled ?50 50 ? a i os output short circuit current [5, 8] v cc = max, v out = 0.5v ?30 ?160 ma i bhl input bus-hold low sustaining current v cc = min, v il = 0.8v +75 ? a i bhh input bus-hold high sustaining current v cc = min, v ih = 2.0v ?75 ? a i bhlo input bus-hold low overdrive current v cc = max +500 ? a i bhho input bus-hold high overdrive current v cc = max ?500 ? a notes 9. dual pins are i/o with jtag pins. 10. for cy37064vp100-143axc, cy37064vp44-143axc; operating range: v cc is 3.3v 0.16v. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 15 of 43 inductance [5] parameter description test conditions 44- pin tqfp 44- pin plcc 100- pin tqfp 160-pin tqfp unit l maximum pin inductance v in = 3.3v at f = 1 mhz 25 8 9nh capacitance [5] parameter description test conditions max unit c i/o input/output capacitance v in = 3.3v at f = 1 mhz at t a = 25c 8 pf c clk clock signal capacitance v in = 3.3v at f = 1 mhz at t a = 25c 12 pf c dp dual functional pins [9] v in = 3.3v at f = 1 mhz at t a = 25c 16 pf endurance characteristics [5] parameter description test conditions min typ unit n minimum reprogramming cycles normal programming conditions [2] 1,000 10,000 cycles ac characteristics figure 7. 5v ac test loads and waveforms figure 8. 3.3v ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 35 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) < 2 ns output 238 ? (com'l) 319 ? (mil) 170 ? (com'l) 236 ? (mil) 99 ? (com'l) 136 ? (mil) equivalent to: thvenin equivalent 2.08v (com'l) 2.13v (mil) 238 ? (com'l) 319 ? (mil) 170 ? (com'l) 236 ? (mil) < 2 ns (c) 5 or 35 pf 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 35 pf including jig and scope 3.3v output 5 pf including jig and scope (a) (b) < 2 ns output 295 ? (com'l) 393 ? (mil) 340 ? (com'l) 453 ? (mil) equivalent to: thvenin equivalent 1.77v (com'l) 1.77v (mil) 295 ? (com'l) 393 ? (mil) 340 ? (com'l) 453 ? (mil) < 2 ns (c) 270 ? (mil) 158 ? (com?l) 5 or 35 pf [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 16 of 43 parameter [11] v x output waveform?measurement level t er(?) 1.5v t er(+) 2.6v t ea(+) 1.5v t ea(?) v the (d) test waveforms v oh v x 0.5v v ol v x 0.5v v x v oh 0.5v v x v ol 0.5v switching characteristics over the operating range [12] parameter description unit combinatorial mode parameters t pd [13, 14, 15] input to combinatorial output ns t pdl [13, 14, 15] input to output through transparent input or output latch ns t pdll [13, 14, 15] input to output through transparent input and output latches ns t ea [13, 14, 15] input to output enable ns t er [11, 13] input to output disable ns input register parameters t wl clock or latch enable input low time [8] ns t wh clock or latch enable input high time [8] ns t is input register or latch set-up time ns t ih input register or latch hold time ns t ico [13, 14, 15] input register clock or latch enable to combinatorial output ns t icol [13, 14, 15] input register clock or latch enable to ou tput through transpa rent output latch ns synchronous clocking parameters t co [14, 15] synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable to output ns t s [13] set-up time from input to sync. clk (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable ns t h register or latch data hold time ns t co2 [13, 14, 15] output synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable to combinatorial output delay (through logic array) ns t scs [13] output synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable to output synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable (through logic array) ns t sl [13] set-up time from input through transparent la tch to output register synchronous clock (clk 0 clk 1 , clk 2 , or clk 3 ) or latch enable ns t hl hold time for input through transparent latch from output register synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable ns [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 17 of 43 product term clocking parameters t copt [13, 14, 15] product term clock or latch enable (ptclk) to output ns t spt set-up time from input to product term clock or latch enable (ptclk) ns t hpt register or latch data hold time ns t ispt [13] set-up time for buried register used as an input register from input to product term clock or latch enable (ptclk) ns t ihpt buried register used as an input register or latch data hold time ns t co2pt [13, 14, 15] product term clock or latch enable (ptclk) to output delay (through logic array) ns pipelined mode parameters t ics [13] input register synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) to output register synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) ns operating frequency parameters f max1 maximum frequency with internal feedback (lesser of 1/t scs , 1/(t s + t h ), or 1/t co ) [5] mhz f max2 maximum frequency data path in output r egistered/latched mode (lesser of 1/(t wl + t wh ), 1/(t s +t h ), or 1/t co ) [5] mhz f max3 maximum frequency with external feedback (lesser of 1/(t co + t s ) or 1/(t wl + t wh ) [5] mhz f max4 maximum frequency in pipelined mode (lesser of 1/(t co + t is ), 1/t ics , 1/(t wl + t wh ), 1/(t is + t ih ), or 1/t scs ) [5] mhz reset/preset parameters t rw asynchronous reset width [5] ns t rr [13] asynchronous reset recovery time [5] ns t ro [13, 14, 15] asynchronous reset to output ns t pw asynchronous preset width [5] ns t pr [13] asynchronous preset recovery time [5] ns t po [13, 14, 15] asynchronous preset to output ns user option parameters t lp low power adder ns t slew slow output slew rate adder ns t 3.3io 3.3v i/o mode timing adder [5] ns jtag timing parameters t s jtag set-up time from tdi and tms to tck [5] ns t h jtag hold time on tdi and tms [5] ns t co jtag falling edge of tck to tdo [5] ns f jtag maximum jtag tap controller frequency [5] ns switching characteristics over the operating range (continued) [12] parameter description unit notes 11. t er measured with 5 pf ac test load and t ea measured with 35 pf ac test load. 12. all ac parameters are measured with two outputs switching and 35 pf ac test load. 13. logic blocks operating in low power mode, add t lp to this specification. 14. outputs using slow output slew rate, add t slew to this specification. 15. when v cco = 3.3v, add t 3.3io to this specification. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 18 of 43 switching characteristics over the operating range [12] parameter 200 mhz 167 mhz 154 mhz 143 mhz 125 mhz 100 mhz 83 mhz 66 mhz unit min max min max min max min max min max min max min max min max combinatorial mode parameters t pd [13, 14, 15] 6 6.5 7.5 8.5 10 12 15 20 ns t pdl [13, 14, 15] 11 12.5 14.5 16 16.5 17 19 22 ns t pdll [13, 14, 15] 12 13.5 15.5 17 17.5 18 20 24 ns t ea [13, 14, 15] 8 8.5 11 13 14 16 19 24 ns t er [11, 13] 8 8.5 11 13 14 16 19 24 ns input register parameters t wl 2.5 2.5 2.5 2.5 3 3 4 5 ns t wh 2.5 2.5 2.5 2.5 3 3 4 5 ns t is 2 222 2 2.5 3 4ns t ih 2 222 2 2.5 3 4ns t ico [13, 14, 15] 11 11 11 12.5 12.5 16 19 24 ns t icol [13, 14, 15] 12 12 12 14 16 18 21 26 ns synchronous clocking parameters t co [14, 15] 4 4 4.5 6 6.5 [16] 6.5 [17] 8 [18] 10 ns t s [13] 44555.5 [16] 6 [17] 8 [18] 10 ns t h 0000 0 0 0 0ns t co2 [13, 14, 15] 9.5 10 11 12 14 16 19 24 ns t scs [13] 5 66.57 8 [16] 10 12 15 ns t sl [13] 7.5 7.5 8.5 9 10 12 15 15 ns t hl 0 000 0 0 0 0ns product term clocking parameters t copt [13, 14, 15] 7101013 13 13 1520ns t spt 2.5 2.5 2.5 3 5 5.5 6 7 ns t hpt 2.5 2.5 2.5 3 5 5.5 6 7 ns t ispt [13] 000 0 00 00n s t ihpt 6 6.5 6.5 7.5 9 11 14 19 ns t co2pt [13, 14, 15] 12 14 15 19 19 21 24 30 ns pipelined mode parameters t ics [13] 56678 [16] 10 12 15 ns operating frequency parameters f max1 200 167 154 143 125 [16] 100 83 66 mhz f max2 200 200 200 167 154 153 [17] 125 [18] 100 mhz f max3 125 125 105 91 83 80 [17] 62.5 50 mhz f max4 167 167 154 125 118 100 83 66 mhz reset/preset parameters t rw 8 8 8 8 10 12 15 20 ns t rr [13] 10 10 10 10 12 14 17 22 ns notes 16. for reference only, the following values correspond to the obsolete cy37512 devices: t co = 5 ns, t s = 6.5 ns, t scs = 8.5 ns, t ics = 8.5 ns, f max1 = 118 mhz. 17. the following values correspond to the cy37192v and cy37256v devices: t co = 6 ns, t s = 7 ns, f max2 = 143 mhz, f max3 = 77 mhz, and f max4 = 100 mhz; and for the cy37512 devices: t s = 7 ns. 18. for reference only, the following values correspond to the obsolete cy37512v devices: t co = 6.5 ns, t s = 9.5 ns, and f max2 = 105 mhz. [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 19 of 43 t ro [13, 14, 15] 12 13 13 14 15 18 21 26 ns t pw 8 8 8 8 10 12 15 20 ns t pr [13] 10 10 10 10 12 14 17 22 ns t po [13, 14, 15] 12 13 13 14 15 18 21 26 ns user option parameters t lp 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t slew 3333 3 3 3 3ns t 3.3io [19] 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns jtag timing parameters t s jtag 0 00 0 00 00n s t h jtag 20 20 20 20 20 20 20 20 ns t co jtag 20 20 20 20 20 20 20 20 ns f jtag 20 20 20 20 20 20 20 20 mhz switching characteristics over the operating range (continued) [12] parameter 200 mhz 167 mhz 154 mhz 143 mhz 125 mhz 100 mhz 83 mhz 66 mhz unit min max min max min max min max min max min max min max min max switching waveforms figure 9. combinatorial output figure 10. registered output with synchronous clocking note 19. only applicable to the 5v devices. t pd input combinatorial output t s input synchronous t co registered output t h synchronous t wl t wh t co2 registered output clock clock [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 20 of 43 figure 11. registered output with product term clocking input going through the array figure 12. registered output with product term clocking input coming from adjacent buried register figure 13. latched output switching waveforms (continued) t spt input product term t copt registered output t hpt clock t ispt input product term t co2pt registered output t ihpt clock t sl input latch enable t co latched output t hl t pdl [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 21 of 43 figure 14. registered input figure 15. clock to clock figure 16. latched input switching waveforms (continued) t is registered input input register clock t ico combinatorial output t ih clock t wl t wh input register clock output register clock t scs t ics t is latched input latch enable t ico combinatorial output t ih t pdl t wl t wh latch enable [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 22 of 43 figure 17. latched input and output figure 18. asynchronous reset switching waveforms (continued) t ics latched input output latch enable latched output t pdll latch enable t wl t wh t icol input latch enable t sl t hl input t ro registered output clock t rr t rw [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 23 of 43 power consumption figure 19. asynchronous preset figure 20. output enable/disable switching waveforms (continued) input t po registered output clock t pr t pw input t er outputs t ea typical 5v power consumption cy37032 0 10 20 30 40 50 60 0 50 100 150 200 250 frequency (mhz) icc (ma) high speed low power the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5v, t a = room temperature [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 24 of 43 cy37064 cy37128 typical 5v power consumption (continued) the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5v, t a = room temperature 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5v, t a = room temperature [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 25 of 43 cy37192 cy37256 typical 5v power consumption (continued) 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5v, t a = room temperature 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5v, t a = room temperature [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 26 of 43 typical 3.3v power consumption cy37032v cy37064v 0 5 10 15 20 25 30 0 20 40 60 80 100 120 140 160 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature 0 5 10 15 20 25 30 35 40 45 0 20 40 60 80 100 120 140 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 27 of 43 cy37128v cy37192v typical 3.3v power consumption (continued) 0 10 20 30 40 50 60 70 80 0 20 40 60 80 100 120 140 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature 0 20 40 60 80 100 120 0 20 40 60 80 100 120 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 28 of 43 cy37256v typical 3.3v power consumption (continued) 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter , per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 29 of 43 pin configurations [20] notes 20. for 3.3v versions (ultra37000v), v cco = v cc . 21. this pin is a n/c, but cypress re commends that you connect it to v cc to ensure future compatibility 44-pin tqfp (a44) top view i/o 2 gnd v cco i/o 3 i/o 4 i/o 1 i/o 0 i/o 29 i/o 30 i/o 31 i/o 28 i/o 27 /tdi i/o 26 i/o 25 i/o 24 clk 1 /i 4 gnd i 3 clk 3 /i 2 i/o 23 i/o 22 i/o 21 gnd i/o 20 v cc i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 12 i/o 5 /tck i/o 6 i/o 7 clk 2 /i 0 gnd clk 0 /i 1 i/o 8 i/o 9 i/o 10 i/o 11 8 9 7 10 11 3 4 2 5 6 1 18 19 20 2221 13 14 15 1716 12 31 30 29 32 33 26 25 24 27 28 23 44 43 42 4041 39 38 37 3536 34 i/o 13 /tms i/o 19 /tdo jtag en 44-pin plcc (j67) top view i/o 27 /tdi i/o 26 i/o 25 i/o 24 clk 1 /i 4 gnd i 3 clk 3 /i 2 i/o 23 i/o 22 i/o 21 i/o 5 /tck i/o 6 i/o 7 clk 2 /i 0 jtag en gnd clk 0 /i 1 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 20 i/o 2 gnd v cco v cc i/o 3 i/o 4 i/o 1 i/o 0 i/o 29 i/o 30 i/o 31 i/o 28 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o 12 65 3 4 2 8 9 7 10 11 44 18 15 16 14 13 12 17 19 20 22 21 23 24 2726 28 25 31 30 29 32 33 34 39 37 38 36 35 43 42 4041 /tms /tdo 1 [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 30 of 43 pin configurations [20] (continued) top view 100-pin tqfp (a100) 100 9798 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 3029 31 32 35 34 36 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 tdi nc v cco i/o 55 i/o 54 i/o 53 i/o 52 clk 3 /i 4 i/o 50 i/o 48 gnd nc i / o 47 i/o 46 i/o 49 gnd tms tck gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 15 v cco gnd clk 1 /i 1 i/o 16 i/o 17 clk 0 /i 0 90 91 i/o 51 v cco clk 2 /i 3 i/o 14 n/c i/o 12 i/o 13 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 gnd nc gnd nc i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 v cco nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 48 49 50 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v cco v cc i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i 2 nc v cco tdo i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 7 6 5 4 3 2 1 v cco i/o 0 v cc nc 63 i/o 62 61 60 59 58 57 56 v cco n/c 99 37 47 [21 ] [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 31 of 43 pin configurations [20] (continued) i/o 77 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 57 147 58 146 59 145 60 144 61 143 62 142 63 141 64 65 66 67 68 140 69 139 70 138 71 137 72 136 73 135 74 134 75 133 76 132 77 131 78 130 79 129 80 128 81 127 82 126 160-pin tqfp (a160) 125 84 83 42 gnd i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 /tck i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 gnd clk 0 /i 0 v cco gnd clk 1 /i 1 gnd gnd gnd gnd gnd v cco i/o 48 i/o 49 i/o 50 i/o 51 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 i 2 v cco v cc i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 71 i/o 72 i/o 73 i/o 74 i/o 75 i/o 78 i/o 79 v cco gnd i/o 80 i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 gnd i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 i/o 96 i/o 97 i/o 98 i/o 99 i/o 100 i/o 101 i/o 102 i/o 103 gnd gnd clk 2 /i 3 v cco clk 3 /i 4 i/o 104 i/o 105 i/o 106 i/o 107 i/o 108 /tdi i/o 109 i/o 110 i/o 111 v cco gnd gnd v cc gnd i/o 112 gnd v cco v cco i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 i/o 122 i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 jtag en i/o 52 /tms i/o 76 /tdo 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 for cy37128(v) and cy37256(v) top view [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 32 of 43 pin configurations [20] (continued) i/o 72 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 57 147 58 146 59 145 60 144 61 143 62 142 63 141 64 65 66 67 68 140 69 139 70 138 71 137 72 136 73 135 74 134 75 133 76 132 77 131 78 130 79 129 80 128 81 127 82 126 160-pin tqfp (a160) for cy37192(v) 125 84 83 42 gnd nc i/o 16 i/o 17 i/o 18 tck i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 gnd clk 0 /i 0 v cco gnd clk 1 /i 1 gnd gnd gnd gnd gnd v cco nc i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i 2 v cco v cc i/o 60 i/o 61 i/o 62 i/o 63 i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 71 i/o 73 i/o 74 v cco gnd nc i/o 75 i/o 76 i/o 77 i/o 78 i/o 79 i/o 80 i/o 81 gnd i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 i/o 96 i/o 97 gnd gnd clk 2 /i 3 v cco clk 3 /i 4 i/o 98 i/o 99 i/o 100 i/o 101 tdi i/o 102 i/o 103 i/o 104 v cco gnd gnd v cc gnd nc gnd v cco v cco i/o 105 i/o 106 i/o 107 i/o 108 i/o 109 i/o 110 i/o 111 i/o 112 i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 nc tms tdo 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 top view [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 33 of 43 pin configurations [20] (continued) 256-ball fine-pitch bga (bb256) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a gn d gn d i/o 2 6 i/o 2 4 i/o 2 0 v cc i/o 1 1 gn d gn d i/o 1 86 v cc i/o 1 77 i/o 1 72 i/o 1 67 gn d gn d b gn d i/o 2 7 i/o 2 5 i/o 2 3 i/o 1 9 i/o 1 5 i/o 1 0 gn d gn d i/o 1 85 i/o 1 81 i/o 1 76 i/o 1 71 i/o 1 66 i/o 1 65 gn d c i/o 2 9 i/o 2 8 nc i/o 2 2 i/o 1 8 i/o 1 4 i/o 9 i/o 4 i/o 1 91 i/o 1 84 i/o 1 80 i/o 1 75 i/o 1 70 nc i/o 1 63 i/o 1 64 d i/o 3 2 i/o 3 1 i/o 3 0 nc i/o 1 7 i/o 1 3 i/o 8 i/o 3 i/o 1 90 i/o 1 83 i/o 1 79 i/o 1 74 i/o 1 69 i/o 1 60 i/o 1 61 i/o 1 62 e i/o 3 5 i/o 3 4 i/o 3 3 i/o 2 1 i/o 1 6 i/o 1 2 i/o 7 i/o 2 i/o 1 89 v cc i/o 1 78 i/o 1 73 i/o 1 68 i/o 1 57 i/o 1 58 i/o 1 59 f v cc i/o 3 8 i/o 3 7 i/o 3 6 tck v cc i/o 6 i/o 1 i/o 1 88 i/o 1 82 v cc tdi i/o 1 54 i/o 1 55 i/o 1 56 v cc g i/o 4 3 i/o 4 2 i/o 4 1 i/o 4 0 v cc i/o 3 9 i/o 5 i/o 0 i/o 1 87 i/o 1 48 i/o 1 49 clk 3 /i 4 i/o 1 50 i/o 1 51 i/o 1 52 i/o 1 53 h gn d gn d i/o 4 7 i/o 4 6 clk 0 /i 0 i/o 4 5 i/o 4 4 gn d gn d i/o 1 44 i/o 1 45 clk 2 /i 3 i/o 1 46 i/o 1 47 gn d gn d j gn d gn d i/o 5 1 i/o 5 0 nc i/o 4 9 i/o 4 8 gn d gn d i/o 1 40 i/o 1 41 i 2 i/o 1 42 i/o 1 43 gn d gn d k i/o 5 7 i/o 5 6 i/o 5 5 i/o 5 4 clk 1 /i 1 i/o 5 3 i/o 5 2 i/o 9 1 i/o 9 6 i/o 1 01 i/o 1 35 v cc i/o 1 36 i/o 1 37 i/o 1 38 i/o 1 39 l v cc i/o 6 0 i/o 5 9 i/o 5 8 tms v cc i/o 8 6 i/o 9 2 i/o 9 7 i/o 1 02 v cc tdo i/o 1 32 i/o 1 33 i/o 1 34 v cc m i/o 6 3 i/o 6 2 i/o 6 1 i/o 7 2 i/o 7 7 i/o 8 2 v cc i/o 9 3 i/o 9 8 i/o 1 03 i/o 1 08 i/o 1 12 i/o 1 17 i/o 1 29 i/o 1 30 i/o 1 31 n i/o 6 6 i/o 6 5 i/o 6 4 i/o 7 3 i/o 7 8 i/o 8 3 i/o 8 7 i/o 9 4 i/o 9 9 i/o 1 04 i/o 1 09 i/o 1 13 nc i/o 1 26 i/o 1 27 i/o 1 28 p i/o 6 8 i/o 6 7 nc i/o 7 4 i/o7 9 i/o 8 4 i/o 8 8 i/o 9 5 i/o 1 00 i/o 1 05 i/o 1 10 i/o 1 14 i/o 1 18 nc i/o 1 24 i/o 1 25 r gn d i/o 6 9 i/o 7 0 i/o 7 5 i/o 8 0 i/o 8 5 i/o 8 9 gn d gn d i/o 1 06 i/o 1 11 i/o 1 15 i/o 1 19 i/o 1 21 i/o 1 23 gn d t gn d gn d i/o 7 1 i/o 7 6 i/o 8 1 v cc i/o 9 0 gn d gn d i/o 1 07 v cc i/o 1 16 i/o 1 20 i/o 1 22 gn d gn d [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 34 of 43 ordering information 5 v ordering information macrocells speed (mhz) ordering code package name package type operating range 32 154 cy37032p44-154axi a44 44-pin pb-free thin quad flat pack industrial 125 CY37032P44-125AXC a44 44-pin pb-free thin quad flat pack commercial cy37032p44-125jxc j67 44-pin pb-free plastic leaded chip carrier 64 125 cy37064p44-125axc a44 44-pin pb-free thin quad flat pack commercial cy37064p44-125jxc j67 44-pin pb-free plastic leaded chip carrier cy37064p100-125axc a100 100-pin pb-free thin quad flat pack cy37064p44-125axi a44 44-pin pb-free thin quad flat pack industrial cy37064p100-125axi a100 100-pin pb-free thin quad flat pack 128 125 cy37128p100-125axc a100 100-pin pb-free thin quad flat pack commercial cy37128p160-125axc a160 160-pin pb-free thin quad flat pack cy37128p100-125axi a100 100-pin pb-free thin quad flat pack industrial cy37128p160-125axi a160 160-pin pb-free thin quad flat pack 100 cy37128p160-100axc a160 160-pin pb-free thin quad flat pack commercial 192 83 cy37192p160-83axc a160 160-pin pb-free thin quad flat pack commercial cy37192p160-83axi a160 160-pin pb-free thin quad flat pack industrial 256 125 cy37256p160-125axc a160 160-pin pb-free thin quad flat pack commercial cy37256p160-125axi a160 160-pin pb-free thin quad flat pack industrial 83 cy37256p160-83axc a160 160-pin pb-free thin quad flat pack commercial cy37256p160-83axi a160 160-pin pb-free thin quad flat pack industrial 3.3 v ordering information macrocells speed (mhz) ordering code package name package type operating range 32 143 cy37032vp44-143axc a44 44-pin pb-free thin quad flat pack commercial 100 cy37032vp44-100axc a44 44-pin pb-free thin quad flat pack 64 100 cy37064vp44-100axc a44 44-pin pb-free thin quad flatpack commercial 128 125 cy37128vp100-125axc a100 100-pin pb-free thin quad flat pack commercial 83 cy37128vp160-83axi a160 160-pin pb-free thin quad flat pack industrial [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 35 of 43 ordering code definitions c y 3 7 128 v p 100 - 125 a x c cypress semiconductor id family type 37 = ultra37000 family macrocell density 32 = 32 macrocells 192 = 192 macrocells 64 = 64 macrocells 256 = 256 macrocells 128 = 128 macrocells speed 200 = 200 mhz 167 = 167 mhz 154 = 154 mhz 143 = 143 mhz 125 = 125 mhz 100 = 100 mhz 83 = 83 mhz 66 = 66 mhz package type a = thin quad flat pack (tqfp) j = plastic leaded chip carrier (plcc) bb = fine-pitch ball grid array (fbga) 1.0 mm lead pitch operating conditions commercial 0c to +70c industrial -40c to +85c operating reference voltage v = 3.3v supply voltage (5.0v if not specified) pin count p44 = 44 pins p100 = 100 pins p160 = 160 pins p256 = 256 pins lead free x = pb free [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 36 of 43 package diagrams figure 21. 44-pin pb-free thin plastic quad flat pack a44 figure 22. 44-pin pb-free plastic leaded chip carrier j67 51-85064 *d 51-85003- *b [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 37 of 43 figure 23. 100-pin pb-free thin plastic quad flat pack (tqfp) a100 51-85048 *d [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 38 of 43 figure 24. 160-pin pb-free thin plastic qu ad flat pack (24 x 24 x 1.4 mm) (tqfp) a160 51-85049 *c [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 39 of 43 figure 25. 256-ball fbga (17 x 17 mm) bb256 51-85108 *h [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 40 of 43 document history page document title: ultra37000 cpld family 5 v and 3.3 v isr? high performance cplds document number: 38-03007 rev. ecn no. submission date orig. of change description of change ** 106272 04/18/01 szv change from spec number: 38-00475 to 38-03007 *a 124942 03/21/03 oor updated 3.3v v cc requirements for ?144 speeds added an addendum *b 126262 05/09/03 teh changed pinout for cy37128v bb100 package *c 128125 07/16/03 hom obsoleted foll owing 3.3v plcc packaged devices: cy37032vp44-143jc cy37032vp44-100jc cy37032vp44-100ji cy37064vp44-143jc cy37064vp84-143jc cy37064vp44-100jc cy37064vp84-100jc cy37064vp44-100ji cy37064vp84-100ji cy37128vp84-125jc cy37128vp84-83jc cy37128vp84-83ji *d 282709 11/08/04 ydt changed package diagrams and labels for consistency added pb-free logo on first page, and a note in features added pb-free package diagram labels added pb-free parts to ordering information cy37032p44-200axc, cy37032p44-200jxc, cy37032p44-154axi, cy37032p44-154jxi, CY37032P44-125AXC, cy37032p44-125jxc, cy37064p44-200axc, cy37064p44- 200jxc, cy37064p100-200axc, cy37064p44-154axi, cy37064p44- 154jxi, cy37064p44-125axc, cy37064p44-125jxc, cy37064p100-125axc, cy37064p44-125axi, cy37064p100-125axi, cy37128p84-167jxc, cy37128p100-167axc, cy37128p160-167axc, cy37128p84-125jxc, cy37128p100-125axc, cy37128p160-125axc, cy37128p84-125jxi, cy37128p100-125axi, cy37128p160-125axi, cy37128p84-100jxc, cy37128p100-100axc, cy37128p160-100axc, cy37128p100- 100axi, cy37192p160-154axc, cy37192p160-125axc, cy37192p160- 125axi, cy37192p160-83axc, cy37192p160-83axi, cy37256p160-154axc, cy37256p160-125axc, cy37256p160-125axi, cy37256p160-83axc, cy37256p160-83axi, cy37032vp44-143axc, cy37032vp44-100axc, cy37032vp44-100axi, cy37032vp44-100jxi, cy37064vp44-143axc, cy37064vp100-143axc, cy37064vp44-100axc, cy37064vp100-100axc, cy37064vp44-100axi, cy37064vp100-100axi, cy37128vp100-125axc, cy37128vp160-125axc, cy37128vp160-125axi, cy37128vp100-83axc, cy37128vp160-83axc, cy37128vp100-83axi, cy37128vp160-83axi, cy37192vp160-100axc, cy37192vp160-66axc, cy37256vp160-100axc, cy37256vp160-100axi, cy37256vp160-66axc *e 321635 03/14/05 pcx added package diagram bg292 updated all pbga package type information (bg292 & bg388) [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 41 of 43 *f 2813051 12/04/09 aae a.in the features section, reduced the maximum number of pins from 400 to 256 in reference to current package pin count in production. b. 5v selection guide: removed cy37384 and cy37512 options from the general information table, removed cy37384 and cy37512 options from the speed bins table, removed all in-active speed bin options, removed all in-active device-package offering and i/o count options. c. 3.3v selection guide: removed cy 37384v and cy37512v options from the general information table, removed cy 37384v and cy37512v options from the speed bins table, removed all in-active speed bin options, removed all in-active device-package offering and i/o count options. d. updated the development software suppor t specific to programming in which the cy3700i (isr programming kit) refere nce had been replaced with the cyusbisrpc programming cable user?s guide. e. logic diagrams: removed referenc es to cy37384/ cy37384v and cy37512/ cy37512v. f. 5v device electrical characteristics specific to the inductance table: removed 44 pin clcc, 84 pin plcc, 84 pin clcc and 208 pin pqfp from the table. g. 3.3v device electrical ch aracteristics specific to th e inductance ta ble: removed 44 pin clcc, 84 pin plcc, 84 pin clcc and 208 pin pqfp from the table. h. note 10: updated cy37064vp100-ac to cy37064vp100-axc and cy37064vp44-143ac to cy37064vp44-143axc. removed references to cy37064vp100-143bbc and cy37064vp48-143 bac because these are obsolete device-package options. i. note 16: removed cy37384 device as a reference. j. note 18: removed cy37384v device as a reference. k. power consumption graphs: removed reference graphs for cy37384, cy37512, cy37384v and cy37512v. l. pin configurations: removed reference pin-outs for 44 pin clcc, 48b fbga, 84 pin plcc, 84 pin clcc, 100b fbga, 160 pin cqfp, 208 pin cqfp, 208 pin pqfp, 292b pbga, 388b pbga, and 400b fbga. m. updated the 5v ordering information: removed the following obsolete part numbers: cy37032p44-200ac, cy37032p 44-200axc, cy37032p44-200jc, cy37032p44-200jxc, cy37032p44 -154ac, cy37032p44-154jc, cy37032p44-154ai, cy37032p44-154ji, cy37032p44-154jxi, cy37032p44-125ac, cy37032p44-125jc, cy37032p44-125ai, cy37032p44-125ji, cy37064p44-200ac, cy37064p44-200axc, cy37064p44-200jc, cy37064p44- 200jxc, cy37064p84-200jc, cy37064p100-200ac, cy37064p44- 154ac, cy37064p44-154jc, cy37064p84-154jc, cy37064p100- 154ac, cy37064p44-154ai, cy37064p44-154ji, cy37064p100-154ai, cy37064p44-125ac, cy37064p44-125jc, cy37064p84- 125jc, cy37064p100-125ac, cy37064p44-125ai, cy37064p44-125ji, cy37064p84-125ji, cy37064p100-125ai, 5962-9951901 qya, cy37128p84-167jc, cy37128p84-167jxc, cy37128p100- 167ac, cy37128p100-167axc, cy37128p160-167ac, cy37128p84- 125jc, cy37128p84-125jxc, cy37128p100-125ac, cy37128p 160-125ac, cy37128p84-125ji, cy37128p84-125jxi, cy37128p100-125ai, cy37128p160-125ai, 5962-9952102qya, cy37128p84-100jc, cy37128p84-100jxc, cy37128p100-100ac, cy37128p 160-100ac, cy37128p84-100ji, cy37128p100-100ai, cy37128p100-100axi, cy37128p160-100ai, 5962-9952101qya, cy37192p160-154ac, cy37192p160-154axc, cy37192p160-125ac, cy37192p 160-125ai, cy37192p160-83ac, cy37192p160-83ai, cy37256p160-154ac, cy37256p160-154axc, cy37256p208-154nc, cy37256p256 -154bgc, cy37256p160-125ac, cy37256p208-125nc, cy37256p256-125bgc, cy37256p160-125ai, cy37256p208-125ni, cy37256p256-125bgi, 5962-9952302qzc, cy37256p160-83ac, cy37256p208- 83nc, cy37256p256-83bgc, document title: ultra37000 cpld family 5 v and 3.3 v isr? high performance cplds document number: 38-03007 rev. ecn no. submission date orig. of change description of change [+] feedback "not recommended for new design"
ultra37000 cpld family document number : 38-03007 rev. *h page 42 of 43 cy37256p160-83ai, cy37256p208-83ni, cy37256p256-83bgi, cy37384p208-125nc, cy37384p256 -125bgc, cy37384p208-83nc, cy37384p256-83bgc, cy37384p 208-83ni, 5962-9952301qzc, cy37384p256-83bg, cy37512p208- 125nc, cy37512p256-125bgc, cy37512p208-100nc, cy37512p256-100bgc, cy37512p352-100bgc, cy37512p208-100ni, cy37512p256-100bgi, cy37512p352-100bgi, 5962-9952502qzc, cy37512p208-83nc, cy37512p256-83bgc, cy37512p352-83bgc, cy37512p208 -83ni, cy37512p256-83bgi, cy37512p352-83bgi, 5962-9952501qzc. n. updated the 3.3v ordering informati on: removed the following obsolete part numbers: cy37032vp44-143ac, cy37032vp48-143bac, cy37032vp44-100ac, cy37032vp48-100bac, cy37032vp44-100ai, cy37032vp44-100axi, cy37032vp48-100bai, cy37032vp44-100ji, cy37032vp44-100jxi, cy37064vp44-143ac, cy37064vp48-143bac, cy37064vp100-143ac, cy37064vp100-143bbc, cy37064vp44-100ac, cy37064vp48-100bac, cy37064vp100-100ac, cy37064vp100-100bbc, cy37064vp44-100ai, cy37064vp44-100axi, cy37064vp48-100bai, cy37064vp100-100bbi, cy37064vp100-100ai, 5962-9952001 qya, cy37128vp100-125ac, cy37128vp100-125bbc, cy37128vp160- 125ac, cy37128vp160-125ai, cy37128vp100-83ac, cy37128vp100-83bbc, cy37128vp160-83ac, cy37128vp100-83ai, cy37128vp100-83bbi, cy37128vp160-83ai, 5962-9952201qya, cy37192vp160-100ac, cy37192vp160-66ac, cy37192vp160-66ai, cy37256vp160 -100ac, cy37256vp208-100nc, cy37256vp256-100bgc, cy37256vp256-100bbc, cy37256vp160-100ai, cy37256vp160-66ac, cy37256vp208-66nc, cy37256vp256-66bgc, cy37256vp160-66ai, cy37256vp256-66bgi, 5962-9952401qzc, cy37384vp208-83nc, cy37384vp256-83bgc, cy37384vp208-66nc, cy37384vp256-66bgc, cy37384vp208-66ni, cy37384vp256-66bgi, cy37512vp208-83nc, cy37512vp256-83bgc, cy37512vp352-83bgc, cy37512vp400-83bbc, cy37512vp208-66nc, cy37512vp256-66bgc, cy37512vp352-66bgc, cy37512vp400-66bbc, cy37512vp208-66ni, cy37512vp256-66bgi, cy37512vp352-66bgi, cy37512vp400-66bbi, 5962-9952601qzc. o. updated package diagram drawing revisions on the following: 51-85064, 51-85003, 51-85048. p. removed package diagram drawing re ferences for obsoleted part numbers: 44 pin clcc (51-80014), 48fbga (51-85109), 84 pin clcc (51-80095), 100b fbga (51-85107), 160 pin cqfp (51-80106), 2 08 pin pqfp (51-85069), 208 pin cqfp (51-80105), 292b pbga (51-85097), 388b pbga (51-85103), 400b fbga (51-85111). q. addendum for 3.3v operating range: updated cy37064vp100-ac to cy37064vp100-axc and cy37064vp44-143ac to cy37064vp44-143axc. removed references to cy37064vp100-143bbc and cy37064vp48-143bac because these are obsolete device-package options. r. removed military operating range becau se all military part numbers have been obsoleted. *g 2896152 03/19/2010 aae removed inactive parts from ordering information. updated table of contents. updated packaging information. updated links in sales, solutions, and legal information. *h 3081920 11/09/2010 aae updated ordering information and ordering code definitions . minor edits. document title: ultra37000 cpld family 5 v and 3.3 v isr? high performance cplds document number: 38-03007 rev. ecn no. submission date orig. of change description of change [+] feedback "not recommended for new design"
document number : 38-03007 rev. *h revised november 09, 2010 page 43 of 43 viewdraw and speedwave are trademarks of viewlogic. windows is a registered trademark of microsoft corporation. warp is a regis tered trademark, and in-system reprogrammable, isr, warp professional, warp enterprise, and ultra37000 are trademarks, of cypress semiconductor corporation. all product and company nam es mentioned in this document are the trademarks of their respective holders. ultra37000 cpld family ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback "not recommended for new design"

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